ARM GIC-400 寄存器

1.简介

GIC-400是用于控制中断的。在cubieboard2 上的A20芯片采用了这款控制器。

cubieboard2 的GIC控制器的地址是0x01C80000—0x01C87FFF ，长度等于GIC-400寄存器的长度。

具体的内容如下所示。

以0x01C80000为起始地址，下面给出的是偏移：

偏移地址	说明
0x0000-0x0FFF	Reserved 未使用，无用
0x1000-0x1FFF	Distributor 配置器有用
0x2000-0x3FFF	CPU interfaces CPU接口有用
0x4000-0x4FFF	Virtual interface control block, for the processor that is performing the access虚拟化相关，无用
0x5000-0x5FFF	Virtual interface control block, for the processor selected by address bits [11:9]虚拟化相关，无用
0x5000-0x51FF0x5200-0x53FF…0x5E00-0x5FFF	Alias for Processor 0Alias for Processor 1…Alias for Processor 7
0x6000-0x7FFF	Virtual CPU interfaces虚拟化相关，无用

常用的是图中第二块和第三块，0x1000~0x3fff这部分的配置。

2.Distributor 配置器

distributor这块寄存器的地址 = GIC控制器的地址 + 0x1000 ，使用的时候别忘记了偏移。然后从这里开始，有如下的寄存器

偏移	名称	可读写	复位后	作用
0x000	GICD_CTLR	RW	0x00000000[c]	Distributor Control Register写入1使能控制器，必备
0x004	GICD_TYPER	RO	Configuration-dependent[d]	Interrupt Controller Type Register其中可以查看中断线的总数
0x008	GICD_IIDR	RO	0x0200143B	Distributor Implementer Identification Register, GICD_IIDR存了一些版本信息，没用
0x080-0x0BC	GICD_IGROUPRn	RW	0x00000000	Interrupt Group Registers[e]一个位图，控制中断属于A组还是B组
0x100	GICD_ISENABLERn	RW[f]	SGIs and PPIs:0x0000FFFF[g]	Interrupt Set-Enable Registers一个位图，用于使能各个中断，写入1使能。有用
0x104-0x13C			SPIs: 0x00000000
0x180	GICD_ICENABLERn	RW[f]	0x0000FFFF[g]	Interrupt Clear-Enable Registers和上一个寄存器类似，作用相反，写入1禁止。
0x184-0x1BC			0x00000000
0x200-0x23C	GICD_ISPENDRn	RW	0x00000000	Interrupt Set-Pending Registerspend位图，写入1可以进入pend状态
0x280-0x2BC	GICD_ICPENDRn	RW	0x00000000	Interrupt Clear-Pending Registers同上，写入1效果相反，阻止pend状态
0x300-0x33C	GICD_ISACTIVERn	RW	0x00000000	Interrupt Set-Active Registers位图，写入1可以激活中断
0x380-0x3BC	GICD_ICACTIVERn	RW	0x00000000	Interrupt Clear-Active Registers写入1反激活中断
0x400-0x5FC	GICD_IPRIORITYRn	RW	0x00000000	Interrupt Priority Registers存着各个中断的优先级，每8位算一个
0x800-0x81C	GICD_ITARGETSRn	RO[h]	-	Interrupt Processor Targets Registers[i]某个中断应该发往哪个处理器进行处理
0x820-0x9FC		RW	0x00000000
0xC00	GICD_ICFGRn	RO	SGIs: 0xAAAAAAAA	Interrupt Configuration Registers, GICD_ICFGRn配置中断是低电平触发还是下降沿触发
0xC04		RO	PPIs: 0x55540000
0xC08-0xC7C		RW[j]	SPIs: 0x55555555
0xD00	GICD_PPISR	RO	0x00000000	Private Peripheral Interrupt Status Register, GICD_PPISR一般没用
0xD04-0xD3C	GICD_SPISRn	RO	0x00000000	Shared Peripheral Interrupt Status Registers, GICD_SPISRn没用
0xF00	GICD_SGIR	WO	-	Software Generated Interrupt Register控制软中断
0xF10-0xF1C	GICD_CPENDSGIRn	RW	0x00000000	SGI Clear-Pending Registers软中断的pend位
0xF20-0xF2C	GICD_SPENDSGIRn	RW	0x00000000	SGI Set-Pending Registers同上，不过写入1时停止pend
0xFD0	GICD_PIDR4	RO	0x00000004	Peripheral ID 4 Register
0xFD4	GICD_PIDR5	RO	0x00000000	Peripheral ID 5 Register
0xFD8	GICD_PIDR6	RO	0x00000000	Peripheral ID 6 Register
0xFDC	GICD_PIDR7	RO	0x00000000	Peripheral ID 7 Register
0xFE0	GICD_PIDR0	RO	0x00000090	Peripheral ID 0 Register
0xFE4	GICD_PIDR1	RO	0x000000B4	Peripheral ID 1 Register
0xFE8	GICD_PIDR2	RO	0x0000002B	Peripheral ID 2 Register
0xFEC	GICD_PIDR3	RO	0x00000000	Peripheral ID 3 Register
0xFF0	GICD_CIDR0	RO	0x0000000D	Component ID 0 Register
0xFF4	GICD_CIDR1	RO	0x000000F0	Component ID 1 Register
0xFF8	GICD_CIDR2	RO	0x00000005	Component ID 2 Register
0xFFC	GICD_CIDR3	RO	0x000000B1	Component ID 3 Register

3.CPU接口

开始地址的偏移量为0x2000

Offset	Name	Type	Reset	Description[a]
0x0000	GICC_CTLR	RW	0x00000000	CPU Interface Control Register使能位。写入1使能
0x0004	GICC_PMR	RW	0x00000000	Interrupt Priority Mask Register限制中断最低优先级，高于此值无法中断，最好写大一点
0x0008	GICC_BPR	RW	0x00000002[b]	Binary Point RegisterThe minimum value of the Binary Point Register depends on which security-banked copy is considered:0x2 Secure copy0x3 Non-secure copy优先级分组
0x000C	GICC_IAR	RO	0x000003FF	Interrupt Acknowledge Register只读，中断id
0x0010	GICC_EOIR	WO	-	End of Interrupt Register写入以告知cpu已经处理完中断
0x0014	GICC_RPR	RO	0x000000FF	Running Priority Register当前中断优先级
0x0018	GICC_HPPIR	RO	0x000003FF	Highest Priority Pending Interrupt Register [c]最高优先级中断号及其pend值
0x001C	GICC_ABPR	RW	0x00000003	Aliased Binary Point Register[d]The minimum value of the Aliased Binary Point Register is 0x3.别名寄存器
0x0020	GICC_AIAR	RO	0x000003FF	Aliased Interrupt Acknowledge Register[d]别名寄存器
0x0024	GICC_AEOIR	WO	-	Aliased End of Interrupt Register[d]别名寄存器
0x0028	GICC_AHPPIR	RO	0x000003FF	Aliased Highest Priority Pending Interrupt Register[c][d]别名寄存器
0x00D0	GICC_APR0	RW	0x00000000	Active Priority Register用于保存和恢复
0x00E0	GICC_NSAPR0	RW	0x00000000	Non-Secure Active Priority Register[d]用于保存和恢复
0x00FC	GICC_IIDR	RO	0x0202143B	CPU Interface Identification Register, GICC_IIDR存着版本信息
0x1000	GICC_DIR	WO	-	Deactivate Interrupt Register