1. Introduction
GIC-400 is used for interrupt control. The A20 chip on the Cubieboard2 uses this controller.
The GIC controller address on Cubieboard2 is 0x01C80000—0x01C87FFF, with a length equal to the GIC-400 register length.
The specific details are shown below.
With 0x01C80000 as the starting address, the following offsets are provided:
| Offset Address | Description |
|---|---|
| 0x0000-0x0FFF | Reserved, unused |
| 0x1000-0x1FFF | Distributor, useful |
| 0x2000-0x3FFF | CPU interfaces, useful |
| 0x4000-0x4FFF | Virtual interface control block, for the processor that is performing the accessVirtualization-related, unused |
| 0x5000-0x5FFF | Virtual interface control block, for the processor selected by address bits [11:9]Virtualization-related, unused |
| 0x5000-0x51FF0x5200-0x53FF…0x5E00-0x5FFF | Alias for Processor 0Alias for Processor 1…Alias for Processor 7 |
| 0x6000-0x7FFF | Virtual CPU interfacesVirtualization-related, unused |
The commonly used parts are the second and third blocks in the diagram, the 0x1000~0x3fff configuration.
2. Distributor
The address of this distributor register block = GIC controller address + 0x1000. Remember this offset when using it. Starting from here, the following registers are available:
| Offset | Name | Access | Reset Value | Function |
|---|---|---|---|---|
| 0x000 | GICD_CTLR | RW | 0x00000000[c] | Distributor Control RegisterWrite 1 to enable the controller, required |
| 0x004 | GICD_TYPER | RO | Configuration-dependent[d] | Interrupt Controller Type RegisterUsed to check the total number of interrupt lines |
| 0x008 | GICD_IIDR | RO | 0x0200143B | Distributor Implementer Identification Register, GICD_IIDRContains version information, not particularly useful |
| 0x080-0x0BC | GICD_IGROUPRn | RW | 0x00000000 | Interrupt Group Registers[e]A bitmap that controls whether interrupts belong to Group A or B |
| 0x100 | GICD_ISENABLERn | RW[f] | SGIs and PPIs:0x0000FFFF[g] | Interrupt Set-Enable RegistersA bitmap for enabling individual interrupts, write 1 to enable. Useful |
| 0x104-0x13C | SPIs: 0x00000000 | |||
| 0x180 | GICD_ICENABLERn | RW[f] | 0x0000FFFF[g] | Interrupt Clear-Enable RegistersSimilar to the previous register, but opposite function, write 1 to disable |
| 0x184-0x1BC | 0x00000000 | |||
| 0x200-0x23C | GICD_ISPENDRn | RW | 0x00000000 | Interrupt Set-Pending RegistersPending bitmap, write 1 to enter pending state |
| 0x280-0x2BC | GICD_ICPENDRn | RW | 0x00000000 | Interrupt Clear-Pending RegistersSimilar to above, write 1 for opposite effect, prevents pending state |
| 0x300-0x33C | GICD_ISACTIVERn | RW | 0x00000000 | Interrupt Set-Active RegistersBitmap, write 1 to activate an interrupt |
| 0x380-0x3BC | GICD_ICACTIVERn | RW | 0x00000000 | Interrupt Clear-Active RegistersWrite 1 to deactivate an interrupt |
| 0x400-0x5FC | GICD_IPRIORITYRn | RW | 0x00000000 | Interrupt Priority RegistersStores priority levels for each interrupt, 8 bits per interrupt |
| 0x800-0x81C | GICD_ITARGETSRn | RO[h] | - | Interrupt Processor Targets Registers[i]Determines which processor an interrupt should be sent to for handling |
| 0x820-0x9FC | RW | 0x00000000 | ||
| 0xC00 | GICD_ICFGRn | RO | SGIs: 0xAAAAAAAA | Interrupt Configuration Registers, GICD_ICFGRnConfigures whether interrupts are level-triggered or falling-edge triggered |
| 0xC04 | RO | PPIs: 0x55540000 | ||
| 0xC08-0xC7C | RW[j] | SPIs: 0x55555555 | ||
| 0xD00 | GICD_PPISR | RO | 0x00000000 | Private Peripheral Interrupt Status Register, GICD_PPISRGenerally not used |
| 0xD04-0xD3C | GICD_SPISRn | RO | 0x00000000 | Shared Peripheral Interrupt Status Registers, GICD_SPISRnNot used |
| 0xF00 | GICD_SGIR | WO | - | Software Generated Interrupt RegisterControls software interrupts |
| 0xF10-0xF1C | GICD_CPENDSGIRn | RW | 0x00000000 | SGI Clear-Pending RegistersPending bits for software interrupts |
| 0xF20-0xF2C | GICD_SPENDSGIRn | RW | 0x00000000 | SGI Set-Pending RegistersSimilar to above, but writing 1 stops pending |
| 0xFD0 | GICD_PIDR4 | RO | 0x00000004 | Peripheral ID 4 Register |
| 0xFD4 | GICD_PIDR5 | RO | 0x00000000 | Peripheral ID 5 Register |
| 0xFD8 | GICD_PIDR6 | RO | 0x00000000 | Peripheral ID 6 Register |
| 0xFDC | GICD_PIDR7 | RO | 0x00000000 | Peripheral ID 7 Register |
| 0xFE0 | GICD_PIDR0 | RO | 0x00000090 | Peripheral ID 0 Register |
| 0xFE4 | GICD_PIDR1 | RO | 0x000000B4 | Peripheral ID 1 Register |
| 0xFE8 | GICD_PIDR2 | RO | 0x0000002B | Peripheral ID 2 Register |
| 0xFEC | GICD_PIDR3 | RO | 0x00000000 | Peripheral ID 3 Register |
| 0xFF0 | GICD_CIDR0 | RO | 0x0000000D | Component ID 0 Register |
| 0xFF4 | GICD_CIDR1 | RO | 0x000000F0 | Component ID 1 Register |
| 0xFF8 | GICD_CIDR2 | RO | 0x00000005 | Component ID 2 Register |
| 0xFFC | GICD_CIDR3 | RO | 0x000000B1 | Component ID 3 Register |
3. CPU Interface
Starting address offset is 0x2000
| Offset | Name | Type | Reset | Description[a] |
|---|---|---|---|---|
| 0x0000 | GICC_CTLR | RW | 0x00000000 | CPU Interface Control RegisterEnable bit. Write 1 to enable |
| 0x0004 | GICC_PMR | RW | 0x00000000 | Interrupt Priority Mask RegisterLimits minimum interrupt priority, interrupts with values above this cannot trigger. Best to set this high |
| 0x0008 | GICC_BPR | RW | 0x00000002[b] | Binary Point RegisterThe minimum value of the Binary Point Register depends on which security-banked copy is considered:0x2 Secure copy0x3 Non-secure copyPriority grouping |
| 0x000C | GICC_IAR | RO | 0x000003FF | Interrupt Acknowledge RegisterRead-only, interrupt ID |
| 0x0010 | GICC_EOIR | WO | - | End of Interrupt RegisterWrite to inform the CPU that interrupt processing is complete |
| 0x0014 | GICC_RPR | RO | 0x000000FF | Running Priority RegisterCurrent interrupt priority |
| 0x0018 | GICC_HPPIR | RO | 0x000003FF | Highest Priority Pending Interrupt Register [c]Highest priority interrupt number and its pending value |
| 0x001C | GICC_ABPR | RW | 0x00000003 | Aliased Binary Point Register[d]The minimum value of the Aliased Binary Point Register is 0x3.Alias register |
| 0x0020 | GICC_AIAR | RO | 0x000003FF | Aliased Interrupt Acknowledge Register[d]Alias register |
| 0x0024 | GICC_AEOIR | WO | - | Aliased End of Interrupt Register[d]Alias register |
| 0x0028 | GICC_AHPPIR | RO | 0x000003FF | Aliased Highest Priority Pending Interrupt Register[c][d]Alias register |
| 0x00D0 | GICC_APR0 | RW | 0x00000000 | Active Priority RegisterUsed for saving and restoring |
| 0x00E0 | GICC_NSAPR0 | RW | 0x00000000 | Non-Secure Active Priority Register[d]Used for saving and restoring |
| 0x00FC | GICC_IIDR | RO | 0x0202143B | CPU Interface Identification Register, GICC_IIDRContains version information |
| 0x1000 | GICC_DIR | WO | - | Deactivate Interrupt Register |